Technical Field
The disclosure relates to a semiconductor storage device in which a plurality of dies or chips are stacked and more particularly to a flash memory equipped with a serial peripheral interface (SPI) function.
Description of Related Art
In a multichip package technique, a plurality of dies or chips of the same type or different types are stacked in one package. For example, the storage capacity may be expanded by stacking memory chips of the same type, or different storage functions may be provided by stacking memory chips of different types. For example, in the non-volatile semiconductor storage device disclosed in Japanese Publication No. 2008-300469, a plurality of memory array chips and control chips for controlling the memory array chips are stacked, and a through electrode of the memory array chips and a through electrode of the control chips are aligned for electrically connecting the two through electrodes. In addition, in the semiconductor device disclosed in Japanese Publication No. 2014-57077, a master flash memory chip and a slave flash memory chip are laminated with a non-core circuit being omitted from the slave flash memory chip, and a signal and a voltage required by operations of device are provided from the master flash memory chip to the flash memory chip.
In a memory device in which a plurality of memory chips are stacked, each memory chip monitors an address output from a host computer and detects whether it is a selected memory chip. The host computer does not need to use a specific command for selecting the memory chip, but outputs a command or an address to a memory device in the same way as processing a monolithic memory chip (hereinafter, the memory device is referred to as a monolithic stacked die).
Additionally, one of the stacked memory chips may be set as a master chip, another one may be set as a slave chip, and the master chip or the slave chip is identified. The master/slave setting may be performed, for example, by a fuse or a metal option. For example, an identification (ID) of the master chip is set to “00”, an ID of the slave chip is set to “01”, the master chip may be selected when BA10=L (i.e., a block address of “10” is L), and the slave chip may be selected when BA10=H.
In this monolithic stacked flash memory, a situation that a period in which the master chip is busy is inconsistent with a period in which the slave chip is busy may occur. For example, problems may include as follows. Although the master chip is not in the busy state, the slave chip is in the busy state, an action instructed by the host computer cannot be performed in the slave chip even if the slave chip is selected according to the address from the host computer.
For example, an NAND flash memory equipped with an SPI function has a status register (SR), the SR stores protection information related to the action or specification of the flash memory or information related to whether the flash memory is in the busy state or the like. The SR may be accessed by a read command or a write command, and the user may write protection information, such as, information related to available areas in the memory array, information related to whether an error correction code is used and information related to protected blocks and so on, in to SR. In a flash memory such as SPI-NAND which does not have a busy/ready pin, the user may be aware of whether the flash memory is in the busy state by reading the SR.
The flash memory is equipped with a function to lock information to be written in the SR or information written into the memory array and with respect to a one-time programming area which fails to be accessed by the user. The one-time programming area is, for example, an area that can store information, such as important parameters related to the operation or specification of the flash memory.
In a condition that the information stored in the SR or the one-time programming area is locked (writing inhibited), a write protect (WP) command is issued from the host computer to the flash memory. The flash memory, if receiving the WP command, sets a specific flag bit (flag bit) assigned to the SR or a fuse register in the one-time programming area to, for example, “1” and thereafter, inhibits the access of the write command configured to rewrite the data in the SR or the one-time programming area. In addition, when executing the WP command, the flash memory programs the lock information set in the fuse register or the protection information program written in the SR to a redundant area in the memory array. Since the fuse register or the SR is volatile, it is necessary to permanently store the lock information or the protection information in a non-volatile redundant area. When the flash memory is again powered on, the protection information or the lock information read from the redundant area is loaded into the SR or the fuse register.
When the read command of the SR is issued from the host computer, the contents of the SR are read from the selected memory chip. In a condition that a monolithic stacked die, since the selection of the memory chip is determined by the address, the SR of each of the master chip and the slave chip must be always the same. Therefore, in the monolithic stacked die, in a condition that the write command is issued from the host computer, the master chip and the slave chip simultaneously execute the write command, and the SR/the one-time programming area is rewritten. In addition, in a condition that the WP command is issued, the master chip and the slave chip also simultaneously execute the WP command, and the fuse register is set to “1” for locking the SR or the one-time programming area.
However, in the operation of such monolithic stacked die, there are issues as follows.
(1) Normally, it is feasible to monitor the busy state of the selected memory chip according to the read command of the SR, but the user is unable to monitor a state of an unselected memory chip. Therefore, a locking operation on the unselected memory chip (including a programming operation on the redundant area) must end earlier than the locking operation on the selected memory chip. Otherwise, even though the unselected memory chip is still busy, the user may obtain the ready state output from the selected memory chip by reading the command. (2) If two memory chips simultaneously execute the WP command, the memory array is simultaneously programmed, such that an operating current (Icc) becomes doubled.